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CODES
2010
IEEE
13 years 5 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
NOSSDAV
2009
Springer
14 years 2 months ago
SLIPstream: scalable low-latency interactive perception on streaming data
A critical problem in implementing interactive perception applications is the considerable computational cost of current computer vision and machine learning algorithms, which typ...
Padmanabhan Pillai, Lily B. Mummert, Steven W. Sch...
ICCAD
2004
IEEE
121views Hardware» more  ICCAD 2004»
14 years 4 months ago
Factoring and eliminating common subexpressions in polynomial expressions
Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
HIPC
2009
Springer
13 years 5 months ago
A performance prediction model for the CUDA GPGPU platform
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...
Kishore Kothapalli, Rishabh Mukherjee, M. Suhail R...
VISUALIZATION
1996
IEEE
13 years 11 months ago
Hierarchical and Parallelizable Direct Volume Rendering for Irregular and Multiple Grids
A general volume rendering technique is described that efficiently produces images of excellent quality from data defined over irregular grids having a wide variety of formats. Re...
Jane Wilhelms, Allen Van Gelder, Paul Tarantino, J...