111 search results - page 18 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
VIS
2007
IEEE
14 years 9 months ago
2007
IEEE
With the exponential growth in size of geometric data, it is becoming increasingly important to make effective use of multilevel caches, limited disk storage, and bandwidth. As a r...
POPL
2009
ACM
14 years 8 months ago
2009
ACM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
DAGSTUHL
2006
13 years 9 months ago
2006
Abstract. The talk focused on a grammar-based technique for identifying redundancy in program code and taking advantage of that redundancy to reduce the memory required to store an...