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» Using Queue Time Predictions for Processor Allocation
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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
CODES
2004
IEEE
13 years 11 months ago
Dynamic overlay of scratchpad memory for energy minimization
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
Manish Verma, Lars Wehmeyer, Peter Marwedel
DAC
1996
ACM
13 years 12 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
13 years 12 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
HPDC
2002
IEEE
14 years 20 days ago
Using Kernel Couplings to Predict Parallel Application Performance
Performance models provide significant insight into the performance relationships between an application and the system used for execution. The major obstacle to developing perfor...
Valerie E. Taylor, Xingfu Wu, Jonathan Geisler, Ri...