466 search results - page 63 / 94 » Using Queue Time Predictions for Processor Allocation |
MICRO
2000
IEEE
14 years 12 hour ago
2000
IEEE
An effective method for reducing the effect of load latency in modern processors is data prefetching. One form of data prefetching, stream buffers, has been shown to be particular...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
WCET
2007
13 years 8 months ago
2007
Our research focuses on formally bounded WCET analysis, where we aim to provide absolute guarantees on execution time bounds. In this paper, we describe how amortisation can be us...
RTAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...