610 search results - page 41 / 122 » Using SAT in QBF |
ATVA
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
PAKDD
2009
ACM
14 years 9 days ago
2009
ACM
Abstract. Over the last decade several prediction methods have been developed for determining structural and functional properties of individual protein residues using sequence and...
PPDP
2009
Springer
14 years 2 months ago
2009
Springer
This paper describes the encoding of a telecommunications feature subscription configuration problem to propositional logic and its solution using a state-of-the-art Boolean sati...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Research in algorithms for Boolean satisfiability and their efficient implementations [26, 8] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks fro...