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» Using a Soft Core in a SoC Design: Experiences with picoJava
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DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 27 days ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
MSE
2005
IEEE
153views Hardware» more  MSE 2005»
14 years 1 months ago
ipPROCESS: Using a Process to Teach IP-Core Development
The reusing of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging System-on-chip (SoC) designs. ...
Marilia Lima, Andre Aziz, Diogo José Costa ...
ISCAS
2005
IEEE
128views Hardware» more  ISCAS 2005»
14 years 1 months ago
Development of an audio player as system-on-a-chip using an open source platform
— Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also red...
Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rai...
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
14 years 8 months ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 4 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...