102 search results - page 12 / 21 » Using embedded FPGAs for SoC yield improvement |
FPL
2003
Springer
14 years 1 months ago
2003
Springer
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
ECRTS
2010
IEEE
13 years 8 months ago
2010
IEEE
The Earliest Deadline First scheduling algorithm (EDF) is known to not be optimal under global scheduling on multiprocessor platforms. Results have been obtained that bound the ma...
TECS
2008
13 years 8 months ago
2008
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...