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GECCO
2004
Springer
182views Optimization» more  GECCO 2004»
14 years 22 days ago
On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
Jörg Langeheine, Martin Trefzer, Daniel Br&uu...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 4 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
14 years 2 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...
SBCCI
2004
ACM
134views VLSI» more  SBCCI 2004»
14 years 23 days ago
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage s...
Gabriella Trucco, Giorgio Boselli, Valentino Liber...
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 4 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky