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ICS
2007
Tsinghua U.
14 years 28 days ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
EMSOFT
2009
Springer
14 years 1 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
HPCA
2007
IEEE
14 years 7 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
DSOM
2005
Springer
14 years 9 days ago
Control Considerations for Scalable Event Processing
The growth in the scale of systems and networks has created many challenges for their management, especially for event processing. Our premise is that scaling event processing requ...
Wei Xu, Joseph L. Hellerstein, Bill Kramer, David ...
EDCC
1999
Springer
13 years 11 months ago
Dependability Modelling and Sensitivity Analysis of Scheduled Maintenance Systems
Abstract. In this paper we present a new modelling approach for dependability evaluation and sensitivity analysis of Scheduled Maintenance Systems, based on a Deterministic and Sto...
Andrea Bondavalli, Ivan Mura, Kishor S. Trivedi