467 search results - page 49 / 94 » Using the DEVS Paradigm to Implement a Simulated Processor |
DSD
2004
IEEE
14 years 16 days ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
VALUETOOLS
2006
ACM
14 years 2 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
ICCAD
1994
IEEE
14 years 28 days ago
1994
IEEE
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
EH
2004
IEEE
14 years 16 days ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...