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    VLSID
    2001
    IEEE
    82views VLSI» more  VLSID 2001»
    High Level Synthesis Of Multi-Precision Data Flow Graphs
    14 years 11 months ago
    High Level Synthesis Of Multi-Precision Data Flow Graphs
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    Vikas Agrawal, Anand Pande, Mahesh Mehendale
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    IPPS
    2007
    IEEE
    115views Distributed And Parallel Com...» more  IPPS 2007»
    High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs
    14 years 5 months ago
    High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs
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    Maik Boden, Thomas Fiebig, Torsten Meibner, Steffe...
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    DATE
    2005
    IEEE
    100views Hardware» more  DATE 2005»
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
    14 years 4 months ago
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
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    Rafael Ruiz-Sautua, María C. Molina, Jos&ea...
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    DATE
    2002
    IEEE
    105views Hardware» more  DATE 2002»
    Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
    14 years 3 months ago
    Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
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    Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
    Chunhong Chen, Majid Sarrafzadeh
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    ASAP
    2000
    IEEE
    96views Hardware» more  ASAP 2000»
    High-Level Synthesis of Nonprogrammable Hardware Accelerators
    14 years 3 months ago
    High-Level Synthesis of Nonprogrammable Hardware Accelerators
    Download  www.hpl.hp.com
    Robert Schreiber, Shail Aditya, B. Ramakrishna Rau...
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