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» Validating High-Level Synthesis
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ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 7 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
IADIS
2004
14 years 9 days ago
Constructing Scorm Compliant Course Based on High Level Petri Nets
With rapid development of the Internet, e-learning system has become more and more popular. Currently, to solve the issue of sharing and reusing of teaching materials in different...
Jun-Ming Su, Shian-Shyong Tseng, Chia-Yu Chen, Jui...
ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
14 years 2 months ago
Automated refinement checking of concurrent systems
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 5 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
DAC
1994
ACM
14 years 3 months ago
Optimizing Resource Utilization and Testability Using Hot Potato Techniques
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
Miodrag Potkonjak, Sujit Dey