428 search results - page 29 / 86 » Validating High-Level Synthesis |
JSS
2010
13 years 5 months ago
2010
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...
DSD
2010
IEEE
13 years 9 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
DAC
2006
ACM
14 years 4 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
ISCAS
2007
IEEE
14 years 5 months ago
2007
IEEE
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
ISSS
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper we discuss, what breakpoints in Source Level Emulationa are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do s...