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CODES
2005
IEEE
14 years 1 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
CODES
2003
IEEE
14 years 1 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
ISCAS
2002
IEEE
153views Hardware» more  ISCAS 2002»
14 years 21 days ago
Biological learning modeled in an adaptive floating-gate system
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
Christal Gordon, Paul E. Hasler
WISE
2002
Springer
14 years 20 days ago
An Update-Risk Based Approach to TTL Estimation in Web Caching
Web caching is an important technique for accelerating web applications and reducing the load on the web server and the network through local cache accesses. As in the traditional...
Jeong-Joon Lee, Kyu-Young Whang, Byung Suk Lee, Ji...
ICDT
2010
ACM
205views Database» more  ICDT 2010»
14 years 18 days ago
On the Aggregation Problem for Synthesized Web Services
The paper formulates and investigates the aggregation problem for synthesized mediators of Web services (SWMs). An SWM is a finite-state transducer defined in terms of templates...
Ting Deng, Wenfei Fan, Leonid Libkin, Yinghui Wu