42 search results - page 2 / 9 » Variable Input Delay CMOS Logic for Low Power Design |
ASAP
2004
IEEE
13 years 10 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
DSD
2004
IEEE
13 years 10 months ago
2004
IEEE
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
ICCD
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...