Sciweavers

163 search results - page 26 / 33
» Variation-aware routing for FPGAs
Sort
View
DAC
2005
ACM
14 years 8 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
14 years 1 months ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
FPL
2003
Springer
128views Hardware» more  FPL 2003»
14 years 23 days ago
Case Study of a Functional Genomics Application
Although microarrays are already having a tremendous impact on biomedical science, they still present great computational challenges. We examine a particular problem involving the...
Tom Van Court, Martin C. Herbordt, Richard J. Bart...
FPGA
2001
ACM
128views FPGA» more  FPGA 2001»
14 years 1 days ago
Using sparse crossbars within LUT
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, bu...
Guy G. Lemieux, David M. Lewis