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ICCAD
2009
IEEE
125views Hardware» more  ICCAD 2009»
13 years 6 months ago
CROP: Fast and effective congestion refinement of placement
Modern circuits become harder to route with the ever decreasing design features. Previous routability-driven placement techniques are usually tightly coupled with the underlying p...
Yanheng Zhang, Chris Chu
ISCAS
2007
IEEE
120views Hardware» more  ISCAS 2007»
14 years 2 months ago
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
Vishwanadh Tirumalashetty, Hamid Mahmoodi
ASPDAC
1998
ACM
119views Hardware» more  ASPDAC 1998»
14 years 20 days ago
Integer Programming Models for Optimization Problems in Test Generation
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
João P. Marques Silva
DATE
2005
IEEE
172views Hardware» more  DATE 2005»
14 years 2 months ago
Evolutionary Optimization in Code-Based Test Compression
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
Ilia Polian, Alejandro Czutro, Bernd Becker
DAC
2005
ACM
13 years 10 months ago
On the need for statistical timing analysis
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...
Farid N. Najm