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» Variation-tolerant circuits: circuit solutions and technique...
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ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
14 years 3 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
14 years 19 days ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
CPAIOR
2007
Springer
14 years 2 months ago
Cost-Bounded Binary Decision Diagrams for 0-1 Programming
Abstract. In recent work binary decision diagrams (BDDs) were introduced as a technique for postoptimality analysis for integer programming. In this paper we show that much smaller...
Tarik Hadzic, John N. Hooker
ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 6 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards
DAC
2009
ACM
14 years 9 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert