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» Variation-tolerant circuits: circuit solutions and technique...
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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 2 months ago
3D floorplanning with thermal vias
Abstract— 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is ...
Eric Wong, Sung Kyu Lim
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 1 months ago
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
Zhong Wang, Jianwen Zhu
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
14 years 23 days ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
BCS
2008
13 years 10 months ago
A Hardware Relaxation Paradigm for Solving NP-Hard Problems
Digital circuits with feedback loops can solve some instances of NP-hard problems by relaxation: the circuit will either oscillate or settle down to a stable state that represents...
Paul Cockshott, Andreas Koltes, John O'Donnell, Pa...
TEC
2002
119views more  TEC 2002»
13 years 8 months ago
Graph-based evolutionary design of arithmetic circuits
Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to ...
Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshik...