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DAC
1991
ACM
13 years 10 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang
IUI
2003
ACM
14 years 9 days ago
Supporting plan authoring and analysis
Interactive tools to help users author plans or processes are essential in a variety of domains. KANAL helps users author sound plans by simulating them, checking for a variety of...
Jihie Kim, Jim Blythe
PEWASUN
2008
ACM
13 years 8 months ago
Modular network trace analysis
In this paper we present EDAT, a tool designed for the analysis of trace files from network simulations and experiments. The EDAT framework encapsulates analysis steps in extensib...
Wolfgang Kieß, Nadine Chmill, Ulrich Wittels...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 1 months ago
Software-friendly HW/SW co-simulation: an industrial case study
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 1 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil