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» Verification of Equivalent-Results Methods
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JISE
1998
106views more  JISE 1998»
13 years 7 months ago
Control / Data-Flow Analysis for VHDL Semantic Extraction
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified....
Yee-Wing Hsieh, Steven P. Levitan
ASPDAC
2001
ACM
107views Hardware» more  ASPDAC 2001»
13 years 11 months ago
An efficient solution to the storage correspondence problem for large sequential circuits
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
INFORMATICALT
2000
123views more  INFORMATICALT 2000»
13 years 7 months ago
Cryptanalysis of the Batch Verifying Multiple RSA Digital Signatures
Recently, Harn proposed an efficient scheme that can batch verification multiple RSA digital signatures. His scheme can reduce signature verification time. However, there is a weak...
Min-Shiang Hwang, Iuon-Chang Lin, Kuo-Feng Hwang
DAC
1996
ACM
13 years 11 months ago
Functional Verification Methodology of Chameleon Processor
- Functional verification of the new generation microprocessor developed by SGS-THOMSON Microelectronics makes extensive use of advanced technologies. This paper presents a global ...
Françoise Casaubieilh, Anthony McIsaac, Mik...
FMCAD
2000
Springer
13 years 11 months ago
A Methodology for Large-Scale Hardware Verification
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...
Mark Aagaard, Robert B. Jones, Thomas F. Melham, J...