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GLVLSI
2003
IEEE
186views VLSI» more  GLVLSI 2003»
14 years 1 months ago
A fast simulation approach for inductive effects of VLSI interconnects
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-D...
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
14 years 1 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
CASES
2003
ACM
14 years 29 days ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
ICES
2003
Springer
103views Hardware» more  ICES 2003»
14 years 28 days ago
Fault Tolerance via Endocrinologic Based Communication for Multiprocessor Systems
The communication mechanism used by the biological cells of higher animals is an integral part of an organisms ability to tolerate cell deficiency or loss. The massive redundancy ...
Andrew J. Greensted, Andrew M. Tyrrell
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
14 years 25 days ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...