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ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 2 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
IPPS
2008
IEEE
14 years 2 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 1 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...