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» Verification-Aware Microprocessor Design
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ASPLOS
2006
ACM
14 years 1 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
LCTRTS
2005
Springer
14 years 1 months ago
Preventing interrupt overload
Performance guarantees can be given to tasks in an embedded system by ensuring that access to each shared resource is mediated by an appropriate scheduler. However, almost all pre...
John Regehr, Usit Duongsaa
IEEEPACT
2008
IEEE
14 years 2 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
CODES
2007
IEEE
14 years 2 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
HIPC
2007
Springer
14 years 1 months ago
FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
The Fast Fourier Transform (FFT) is of primary importance and a fundamental kernel in many computationally intensive scientific applications. In this paper we investigate its perf...
David A. Bader, Virat Agarwal