21 search results - page 1 / 5 » Verifying Properties Using Sequential ATPG |
ITC
2002
IEEE
14 years 20 days ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
IOLTS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...