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» Verifying VLSI Circuits
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ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 8 months ago
Integrated circuit design with NEM relays
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King L...
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
14 years 5 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
14 years 5 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 5 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
DAC
2006
ACM
15 years 5 days ago
Circuit simulation based obstacle-aware Steiner routing
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing t...
Yiyu Shi, Paul Mesa, Hao Yu, Lei He