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» Verifying VLSI Circuits
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GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
14 years 2 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
14 years 2 months ago
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
Vishal Suthar, Shantanu Dutt
ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
14 years 2 months ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
SBCCI
2005
ACM
80views VLSI» more  SBCCI 2005»
14 years 2 months ago
On the design of very small transconductance OTAs with reduced input offset
In this paper it will be demonstrated, from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without d...
Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Mo...