Sciweavers

1093 search results - page 127 / 219
» Verifying VLSI Circuits
Sort
View
SBCCI
2004
ACM
100views VLSI» more  SBCCI 2004»
14 years 2 months ago
Design of RF CMOS low noise amplifiers using a current based MOSFET model
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
Virgínia Helena Varotto Baroncini, Oscar da...
ISMVL
2003
IEEE
83views Hardware» more  ISMVL 2003»
14 years 2 months ago
Multiple-Valued Dynamic Source-Coupled Logic
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evalua...
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyam...
VTS
2002
IEEE
101views Hardware» more  VTS 2002»
14 years 1 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
14 years 1 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas
EVOW
1999
Springer
14 years 1 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...