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» Verifying VLSI Circuits
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VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 9 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P...
DFT
2007
IEEE
109views VLSI» more  DFT 2007»
14 years 3 months ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...
ISQED
2006
IEEE
136views Hardware» more  ISQED 2006»
14 years 2 months ago
An Improved AMG-based Method for Fast Power Grid Analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
Cheng Zhuo, Jiang Hu, Kangsheng Chen
ISCAS
2005
IEEE
114views Hardware» more  ISCAS 2005»
14 years 2 months ago
Performance analysis by topology indexed lookup tables
— Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, ...
P. Agarwal, A. Vidyarthi, Patrick H. Madden
SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
14 years 2 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...