Architecture and Design of a High Performance SRAM for SOC Design

Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropriate circuit partitioning, transistor sizing, choice of a suitable Sense Amplifier, a good resetting technique and judicial use of dual Vth transistors we have achieved a high speed memory without dissipating too much power.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout
• Keywords: Computer Architecture, Dual Vth Transistors, Power Static Ram, VLSID 2002