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» Verifying VLSI Circuits
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ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
14 years 5 months ago
Precomputation-based Guarding for Dynamic and Leakage Power Reduction
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, I...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
14 years 2 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...
EUROCAST
2001
Springer
106views Hardware» more  EUROCAST 2001»
14 years 1 months ago
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata
CAST.FSM denotes a CAST tool which has been developed at the Institute of Systems Science at the University of Linz during the years 1986-1993. The first version of CAST.FSM was i...
Michael Affenzeller, Franz Pichler, Rudolf Mittelm...
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
14 years 1 months ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
14 years 1 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong