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» Verifying VLSI Circuits

15

DFT
2007
IEEE

100views VLSI» more DFT 2007»

Soft Error Hardening for Asynchronous Circuits

14 years 1 months ago

Soft Error Hardening for Asynchronous Circuits

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Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao

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17

DFT
2005
IEEE

92views VLSI» more DFT 2005»

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits

14 years 1 months ago

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits

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Jia Di, Parag K. Lala, D. P. Vasudevan

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20

ISVLSI
2003
IEEE

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Fast and Precise Power Prediction for Combinational Circuits

14 years 23 days ago

Fast and Precise Power Prediction for Combinational Circuits

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Hongping Li, John K. Antonio, Sudarshan K. Dhall

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23

IJCNN
2007
IEEE

133views Neural Networks» more IJCNN 2007»

Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit

14 years 1 months ago

Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit

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—The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35µm CMOS technology. The fir...

Jayawan H. B. Wijekoon, Piotr Dudek

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25

VLSID
1995
IEEE

97views VLSI» more VLSID 1995»

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

13 years 11 months ago

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Download www1.cs.columbia.edu

In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free

Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng

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