1093 search results - page 155 / 219 » Verifying VLSI Circuits |
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode insertion and jumper in...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...