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» Verifying VLSI Circuits
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ICCAD
2006
IEEE
106views Hardware» more  ICCAD 2006»
14 years 5 months ago
Wire density driven global routing for CMP variation and timing
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
14 years 5 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra
ISPD
2010
ACM
177views Hardware» more  ISPD 2010»
14 years 3 months ago
Skew management of NBTI impacted gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
Ashutosh Chakraborty, David Z. Pan
ISPD
2010
ACM
157views Hardware» more  ISPD 2010»
14 years 3 months ago
SafeChoice: a novel clustering algorithm for wirelength-driven placement
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...
Jackey Z. Yan, Chris Chu, Wai-Kei Mak
ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
14 years 3 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...