1093 search results - page 189 / 219 » Verifying VLSI Circuits |
VTS
2008
IEEE
14 years 3 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
VTS
2008
IEEE
14 years 3 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
IJCNN
2007
IEEE
14 years 3 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
ISVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
ISVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...