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» Verifying VLSI Circuits
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VLSID
1994
IEEE
103views VLSI» more  VLSID 1994»
13 years 11 months ago
GLOVE: A Graph-Based Layout Verifier
Cyrus Bamji, Jonathan Allen
GLVLSI
2010
IEEE
178views VLSI» more  GLVLSI 2010»
14 years 9 days ago
Improving the testability and reliability of sequential circuits with invariant logic
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
JCSC
2002
129views more  JCSC 2002»
13 years 7 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
14 years 2 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
VLSID
2004
IEEE
168views VLSI» more  VLSID 2004»
14 years 7 months ago
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful...
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Nam...