1093 search results - page 39 / 219 » Verifying VLSI Circuits |
EURODAC
1995
IEEE
14 years 9 days ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
DFT
1997
IEEE
14 years 29 days ago
1997
IEEE
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...
GLVLSI
2003
IEEE
14 years 2 months ago
2003
IEEE
The characterization as well as the control of the electromagnetic emission of integrated circuits is an important step in the design process of state of the art integrated circui...