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» Verifying VLSI Circuits
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VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
14 years 10 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
VLSID
2001
IEEE
169views VLSI» more  VLSID 2001»
14 years 10 months ago
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, ...
GLVLSI
2009
IEEE
92views VLSI» more  GLVLSI 2009»
14 years 4 months ago
Online circuit reliability monitoring
In this work we propose an online reliability tracking framework that utilizes a hybrid network of on-chip temperature and delay sensors together with a circuit reliability macrom...
Bin Zhang
GLVLSI
2003
IEEE
145views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Using dynamic domino circuits in self-timed systems
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
Jung-Lin Yang, Erik Brunvand
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
14 years 2 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...