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» Verifying VLSI Circuits
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GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
DAC
1998
ACM
14 years 11 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
14 years 4 months ago
Characterisation of FPGA Clock Variability
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
ISVLSI
2007
IEEE
205views VLSI» more  ISVLSI 2007»
14 years 4 months ago
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
Angan Das, Ranga Vemuri