1093 search results - page 77 / 219 » Verifying VLSI Circuits |
ICCD
1999
IEEE
14 years 2 months ago
1999
IEEE
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
VLSID
1996
IEEE
14 years 2 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
VLSID
2010
IEEE
14 years 1 months ago
2010
IEEE
—We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET. The model is based on the EKV formalism and is valid in all r...
FCCM
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...
CATA
2007
13 years 11 months ago
2007
In this paper, Simulated Evolution based goodness attributes are incorporated into Tabu Search and Genetic Algorithms to enhance performance as compared to canonical strategies. I...