1093 search results - page 82 / 219 » Verifying VLSI Circuits |
VLSID
2007
IEEE
14 years 10 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
VTS
2002
IEEE
14 years 2 months ago
2002
IEEE
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
FORMATS
2006
Springer
14 years 1 months ago
2006
Springer
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
ASPDAC
2008
ACM
14 years 23 hour ago
2008
ACM
This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...