1093 search results - page 92 / 219 » Verifying VLSI Circuits |
ASPDAC
2006
ACM
14 years 4 months ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
ISLPED
2006
ACM
14 years 4 months ago
2006
ACM
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
ASPDAC
2001
ACM
14 years 1 months ago
2001
ACM
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
CONCUR
1998
Springer
14 years 2 months ago
1998
Springer
In this paper we solve the following problem: \given a digital circuit composed of gates whose real-valued delays are in an integerbounded interval, is there a way to discretize ti...
ATVA
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...