Sciweavers

222 search results - page 15 / 45
» Verifying an Arbiter Circuit
Sort
View
GLVLSI
2010
IEEE
178views VLSI» more  GLVLSI 2010»
14 years 23 days ago
Improving the testability and reliability of sequential circuits with invariant logic
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
ANCS
2006
ACM
14 years 1 months ago
Localized asynchronous packet scheduling for buffered crossbar switches
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspo...
Deng Pan, Yuanyuan Yang
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 5 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
14 years 2 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
ASIACRYPT
2010
Springer
13 years 6 months ago
Short Non-interactive Zero-Knowledge Proofs
We show that probabilistically checkable proofs can be used to shorten non-interactive zero-knowledge proofs. We obtain publicly verifiable non-interactive zero-knowledge proofs fo...
Jens Groth