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» Verifying an Arbiter Circuit
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IPPS
2010
IEEE
13 years 5 months ago
Prototype for a large-scale static timing analyzer running on an IBM Blue Gene
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
Akintayo Holder, Christopher D. Carothers, Kerim K...
DAC
2007
ACM
14 years 9 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
FMSD
2010
118views more  FMSD 2010»
13 years 6 months ago
On simulation-based probabilistic model checking of mixed-analog circuits
In this paper, we consider verifying properties of mixed-signal circuits, i.e., circuits for which there is an interaction between analog (continuous) and digital (discrete) values...
Edmund M. Clarke, Alexandre Donzé, Axel Leg...
DAC
2006
ACM
14 years 9 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 8 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann