Sciweavers

222 search results - page 28 / 45
» Verifying an Arbiter Circuit
Sort
View
DAC
2003
ACM
14 years 9 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
14 years 2 months ago
High Read Stability and Low Leakage Cache Memory Cell
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
Zhiyu Liu, Volkan Kursun
ISCAS
2007
IEEE
91views Hardware» more  ISCAS 2007»
14 years 2 months ago
Power Harvesting With PZT Ceramics
—Piezoelectric materials have been proposed as embedded power source, which are capable of converting mechanical energy into electrical energy. However, power generated from a pi...
Hong Chen, Chen Jia, Chun Zhang, Zhihua Wang, Chun...
DAC
2006
ACM
14 years 1 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao