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» Very Compact FPGA Implementation of the AES Algorithm
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IOLTS
2002
IEEE
148views Hardware» more  IOLTS 2002»
14 years 10 days ago
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reco...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
JSA
2007
142views more  JSA 2007»
13 years 7 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
DAC
2010
ACM
13 years 11 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
CHES
2004
Springer
106views Cryptology» more  CHES 2004»
13 years 11 months ago
XTR Implementation on Reconfigurable Hardware
Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F p6 with order dividing p2 -p+1 by their trace over Fp2 ....
Eric Peeters, Michael Neve, Mathieu Ciet
FCCM
2006
IEEE
137views VLSI» more  FCCM 2006»
14 years 1 months ago
Single Pass, BLAST-Like, Approximate String Matching on FPGAs
Abstract: Approximate string matching is fundamental to bioinformatics, and has been the subject of numerous FPGA acceleration studies. We address issues with respect to FPGA imple...
Martin C. Herbordt, Josh Model, Yongfeng Gu, Bhara...