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» Very Compact FPGA Implementation of the AES Algorithm
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FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
13 years 11 months ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 2 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
13 years 11 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
CHES
2006
Springer
81views Cryptology» more  CHES 2006»
13 years 11 months ago
Template Attacks in Principal Subspaces
Side-channel attacks are a serious threat to implementations of cryptographic algorithms. Secret information is recovered based on power consumption, electromagnetic emanations or ...
Cédric Archambeau, Eric Peeters, Fran&ccedi...
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi