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ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
13 years 12 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...
INFOCOM
1997
IEEE
13 years 12 months ago
Design of a Gigabit ATM Switch
This paper describes the design and implementation of a gigabit ATM switching system supporting link rates from 150 Mb/s to 2.4 Gb/s, with a uniquely e cient multicastswitch archi...
Thomas J. Chaney, J. Andrew Fingerhut, Margaret Fl...
CAL
2007
13 years 7 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
HPCA
2012
IEEE
12 years 3 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...