- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
We exhibit an explicitly computable ‘pseudorandom’ generator stretching l bits into m(l) = lΩ(log l) bits that look random to constant-depth circuits of size m(l) with log m...
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob...
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...