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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 12 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
COCO
2005
Springer
130views Algorithms» more  COCO 2005»
13 years 9 months ago
Pseudorandom Bits for Constant Depth Circuits with Few Arbitrary Symmetric Gates
We exhibit an explicitly computable ‘pseudorandom’ generator stretching l bits into m(l) = lΩ(log l) bits that look random to constant-depth circuits of size m(l) with log m...
Emanuele Viola
ICCAD
2010
IEEE
121views Hardware» more  ICCAD 2010»
13 years 5 months ago
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob...
DAC
2003
ACM
14 years 8 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim