248 search results - page 10 / 50 » Virtual Symmetry Reduction |
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
Research in algorithms for Boolean satisfiability and their efficient implementations [26, 8] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks fro...
SC
1993
ACM
14 years 1 months ago
1993
ACM
A deadlock-free fully adaptive routing algorithm for 2D meshes which is optimal in the number of virtual channels required and in the number of restrictions placed on the use of t...
ACMACE
2007
ACM
14 years 1 months ago
2007
ACM
Fundamental to the generation of 3D audio is the HRTF processing of acoustical signals. Unfortunately, given the high dimensionality of HRTFs, incorporating them into dynamic/inte...
ICCD
2003
IEEE
14 years 6 months ago
2003
IEEE
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...